XOR Gate Verilog Behavioral

Two Input XOR Function (Behavioral Style)

Design Code
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module xor_function(output f, input a, b);
  wire f;
  assign f = a^b;  // Bit-wise operator
endmodule
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Test Bench
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module xor_test;
  reg x, y;
  wire z;
  xor_function F1 (.a(x), .b(y), .f(z)); //Another way of mapping ports
  initial
    begin
      $monitor("a=%b b=%b f=%b", x,y,z);  //
      x = 1'b0; y = 1'b0;
      #5 x = 1'b0; y = 1'b1;
      #5 x = 1'b1; y = 1'b0;
      #5 x = 1'b1; y = 1'b1;
      $finish;
    end
endmodule
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1. Operators
  • Bit-wise Operators
  • Arithmetic Operators
  • Logical Operators
  • Reduction operators
  • Shift operators
  • Relational Operators
  • Conditional operators

Bit-wise Operators (Basically used with assign statement)
    • & : Bitwise AND operator
    • |   : Bitwise OR operator
    • ^  : Bitwise XOR operator
    • ~  : Bitwise NOT operator
    • ~^: Bitwise XNOR operator
    • E.g. 3 input xor function is represented as assign f = a^b^c;

2. Instantiation
  • There are two ways of mapping port signals during instantiation
    • Order-wise mapping
    • One-to-one mapping (irrespective of order)
  • In order-wise mapping/connection, signals in instantiation list are specified in same order as specified in called module. e.g. xor_function F1 (z, x, y); here z is mapped to output f, x and y are mapped to inputs a and b respectively.
  • One-to-one mapping/connection, the signals in instantiation list can be specified in random order using one-to-one association. e.g. xor_function F1 (.a(x), .b(y), .f(z)); here x, y and z are associated with a, b and f respectively. 



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