OR Gate Verilog Behavioral

Two Input OR Function



Design Code (Behavioral style)
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module or_function(output f, input a, b);   // type of variable is declared inside module parameter lists

  wire f;

  assign f = a|b;

endmodule
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Test Bench code

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module or_test;

  reg x, y;  //because these are used in left side in initial blocks 

  wire z;   // since is a not used in left side in initial block, it could be wire type

  or_function F1 (z, x, y);

  initial

    begin

      $monitor("a=%b b=%b f=%b", x,y,z);  // $monitor directive: print whenever there is change in x, y, z

      x = 1'b0; y = 1'b0;  // single bit of binary 0

      #5 x = 1'b0; y = 1'b1;

      #5 x = 1'b1; y = 1'b0;

      #5 x = 1'b1; y = 1'b1;

      $finish;

    end

endmodule

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Output

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a=0 b=0 f=0

a=0 b=1 f=1

a=1 b=0 f=1

a=1 b=1 f=1

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1. $monitor directive

• It displays whenever there is change in any variable in the variable list.

2. 1'b0

• It is a way of representing a number
• <size>'<base><no.>
• 1'b0 means 1 bit wide, binary 0
• similarly 3'b010 means 3 bit wide binary 010 
• 3'b111 = 3'o7 octal representation
• 8'b11110000 = 4'hF0 hexa representation