HALF ADDER UDP Style Verilog

HALF ADDER (User Defined Primitive (UDP) Style)


  • Behavioral/Functional Codes can be expressed in a form of Boolean expression (Data flow type (assign)) and in form of truth tables (Using UDP).
  • So UDP tables also defines the behavior/functionality of a system.
  • In both cases, only behavior of circuit is expressed.
  • It doesn't tell about the internal circuit design i.e. which gates are used normal logical gates or universal gates, how they are interconnected or at transistor level how transistors are interconnected.  


_______________________________________________________________________________
primitive HA_sum(Sum, a, b);   // Similar to module, output 1st, then inputs
input a, b;
output Sum; // for combinational ckt, output must be of output type
table
  // a b : sum  // input's order must be same
     0 0 :  0;
     0 1 :  1;
     1 0 :  1;
     1 1 :  0;
endtable
endprimitive

primitive HA_Cout(Cout, a, b);  // For each output, separate UDP is defined
input a, b;
output Cout;
table
  // a b : Cout
     0 0 :  0;
     0 1 :  0;
     1 0 :  0;
     1 1 :  1;
endtable
endprimitive
_______________________________________________________________________________

Test Bench

_______________________________________________________________________________
module HA_test;
  reg a,b;
  wire Sum, Cout;
  HA_sum HA1 (Sum, a, b);   // Instantiation
  HA_Cout (Cout, a, b); // Instantiation, name is optional
  initial
    begin
      $display("a b \t Sum Carry");
      $monitor("%b %b \t  %b    %b", a,b,Sum,Cout);
      a=1'b0; b=1'b0;
      #5 a=1'b0; b=1'b1;
      #5 a=1'b1; b=1'b0;
      #5 a=1'b1; b=1'b1;
      #5 $finish;
    end
endmodule
_________________________________________________________________________________


Output
________________________
a b Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
_________________________


User Defined Primitive (UDP)

  • It is used to define truth table and state table.
  • Each UDP can be used to implement single function (or single output).
  • No vector declaration.
  • In port list, a single output variable is written first, then input variables are mentioned.
  • Syntax for truth table: <inputs> : <output>
  • Inputs must be mentioned in same order as in port list.
  • For combinational circuit, output is declared as output.
  • For sequential circuit, output is declared as reg.
  • Default output is x (don't care)
  • At max 10 input variables can be defined for combinational ckt and 9 input variables can be defined for sequential ckt.


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