Half Adder (Structural Design) Verilog

Half Adder (Structural Design)


  • Structural Design can be defined at gate and transistor level (using built-in-primitives) and at functional level or combination of these three styles.
  • For gate level modelling, predefined logic gates (and, nand, or, nor, xor, xnor, buf, not) are used via their instantiation.
    • syntax: <predefined_gate> <instance_name> (list_of_ports);
    • e.g. and G1 (f, a, b, c);
    • syntax: <predefined_gate> <instance_name>[N:0] (list_of_ports);
    • or G[1:0] (f, a, b, c);  It makes two instances of 3-Input OR gate with name G1 and G0.
  • For transistor level modelling, predefined switches (tran, rtran, nmos, pmos, rnmos, rpmos, cmos, rcmos, rtranif0, rtranif1, tranif0, tranif1) are used via their instantiation.


Design Code (Structural Modelling)
_________________________________________________________________________________

module Half_Adder(output Sum, Cout, input a, b);
  xor G1 (Sum, a, b);  // instantiation of predefined and gate
  and G2 (Cout, a, b); // instantiation of predefined xor gate
endmodule
_________________________________________________________________________________

Test Bench
_________________________________________________________________________________
module HA_test;
  reg a,b;
  wire Sum, Cout;
  Half_Adder HA1 (Sum, Cout, a, b);
  initial
    begin
      $display("a b \t Sum, Carry");
      $monitor("%b %b \t  %b     %b", a,b,Sum,Cout);
      a=1'b0; b=1'b0;
      #5 a=1'b0; b=1'b1;
      #5 a=1'b1; b=1'b0;
      #5 a=1'b1; b=1'b1;
      #5 $finish;
    end
endmodule
_________________________________________________________________________________

Output
______________________________
a b Sum, Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
______________________________


Design Code 2
_________________________________________________________________________________

module Half_Adder(output Sum, Cout, input a, b);
  xor #2 G1 (Sum, a, b);  // with Delay (assume delay of two NAND gate)
  and #3 G2 (Cout, a, b); // assume delay of 3 NAND gate
endmodule
_________________________________________________________________________________

Test Bench 2
_________________________________________________________________________________
module HA_test;
  reg a,b;
  wire Sum, Cout;
  Half_Adder HA1 (Sum, Cout, a, b);
  initial
    begin
      $display("\t\t Time \t a b \t Carry Sum");
      $monitor($time,"\t %b %b \t  %b     %b", a,b,Cout,Sum);
      a=1'b0; b=1'b0;
      #5 a=1'b0; b=1'b1;
      #5 a=1'b1; b=1'b0;
      #5 a=1'b1; b=1'b1;
      #5 $finish;
    end
endmodule
_________________________________________________________________________________


Output
______________________________________________________
                              Time a b Carry Sum
0 0 0 z z
2 0 0 0 z
3 0 0 0 0
5 0 1 0 0
8 0 1 0 1
10 1 0 0 1
15 1 1 0 1
17 1 1 1 1
18 1 1 1 0
_______________________________________________________
default value of  wire (net) is 'z'

  • A delay can be specified with a predefined gates.
    • e.g. and #2 G1 (Sum, a, b);
  • Similarly signal strength can be defined with predefined gates.
    • e.g. and (strong1, weak0) (Sum, a, b);
    • e.g. and (strong1, weak0) #2 (Sum, a, b);
  • Sum is changed after a delay of 2 units.
  • Carry is changed after a delay of 3 units.



Truth Table of Predefined logic gates

  • x is don't care
  • z is high impedance state

and G1 (f, a, b);
a  b f
0 0 0
0 1 0
1 0 0
1 1 1
0 x,z 0
1,x,z x,z x





or G1 (f, a, b);
a  b f
0 0 0
0 1 1
1 0 1
1 1 1
1 x,z 1
0,x,z x,z x





xor G1 (f, a, b);
a  b f
0 0 0
0 1 1
1 0 1
1 1 0
0,1,x,z x,z x


anand G1 (f, a, b);
a  b f
0 0 1
0 1 1
1 0 1
1 1 0
0 x,z 1
1,x,z x,z x


nor G1 (f, a, b);
a  b f
0 0 1
0 1 0
1 0 0
1 1 0
1 x,z 0
0,x,z x,z x



xnor G1 (f, a, b);
a bf
001
010
100
111
0,1,x,zx,z
x




Comments

Post a Comment

Popular posts from this blog

16-to-1 multiplexer (16X1 MUX) Verilog

Image
Bottom-UP Hierarchical Structure Structure modeling of 2-to-1 MUX 4-to-1 MUX using two 2-to-1 MUX 8-to-1 MUX using two 4-to-1 MUX 16-to-1 MUX usng two 8-to-1 MUX   1. Structural Modeling of 2-to-1 MUX Design Code _________________________________________________________________________________ module MUX_2X1(input I0, I1, S, output Y);   wire sbar, w1, w2, Y;   not G1 (sbar, S);   and G2 (w1, I0, sbar);   and G3 (w2, I1, S);   or G4 (Y, w1, w2); endmodule _________________________________________________________________________________ Test Bench _________________________________________________________________________________ module MUX_test;  reg [2:0] x;    wire z;   MUX_2X1 M1 (x[0], x[1], x[2], z);    initial      begin           $display("\t\t Time\tSelect  A B \t Z");           $monitor($time,"\t %b \t%b %b \t %b", x[2], x[0], x[1], z);           x = 3'O0;       #5 x = 3'O1;  
Read more

8 bit Adder Verilog

Image
Eight bit Adder By cascading of two - 4-bit Adders Design Code _________________________________________________________________________________  module Adder_8bit(input [7:0] A, B, input Cin, output [7:0] S, output Cout);   wire Cout1;   Adder_4bit ADD1 (A[3:0], B[3:0], Cin, S[3:0], Cout1);   Adder_4bit ADD2 (A[7:4], B[7:4], Cout1, S[7:4], Cout); endmodule   module Adder_4bit(input [3:0] A, B, input C0, output [3:0] S, output C4);   wire C1, C2, C3;   Full_adder FA0 (S[0], C1, A[0], B[0], C0);   Full_adder FA1 (S[1], C2, A[1], B[1], C1);   Full_adder FA2 (S[2], C3, A[2], B[2], C2);   Full_adder FA3 (S[3], C4, A[3], B[3], C3); endmodule module Full_adder(output S, C1, input A, B, C0);   wire w1, w2, w3;   Half_Adder HA1 (w1, w2, A, B);   Half_Adder HA2 (S, w3, w1, C0);   or_function G1 (C1, w2, w3); endmodule module Half_Adder(output S, C, input A, B);   xor G1 (S, A, B);   and G2 (C, A, B); endmodule module or_function(output f, input a, b);    o
Read more

Carry Lookahead 4-bit Adder Verilog

Image
Logic Diagram for Sums  Logic Diagram for Carries There are two important variables in Carry lookahead Adder Carry Generate Component Gi: It state that output carry Ci+1 is generated irrespective input carry Ci. This state occurs when both inputs Ai and Bi are 1. so Gi = Ai.Bi Carry Propagate Component Pi: It state that input carry Ci is propagated to output carry Ci+1. In other words, in this state the output carry Ci+1 is equal to input carry Ci. This state occurs when either of input is 1, other is 0. (or One input is compliment of other input). So Pi = Ai^Bi Overall equation for output carry Ci+1 = Gi + Pi.Ci (in other words, Cout = A0.B0 + (A0^B0).Cin) Sum = (Ai^Bi)^Ci = Pi^Ci Design Code _________________________________________________________________________________  module Carry_Lookahead_Adder(a,b,cin,sum,cout);   input[3:0] a,b; input cin;   output [3:0] sum; output cout;   wire p0,p1,p2,p3,g0,g1,g2,g3,c1,c2,c3;   assign p0=(a[0]^b[0]), p1=
Read more