Gates via Verilog


Example 1: Two input AND Function

____________________________________________________________________________
// Design code

module and_function(f, a, b);   // Each statement is end with ';' just like used in C language
  input a, b;                        // declaration command, a and b are defined as input ports
  output f;                         // f is declared as output port
  wire f;                           // wire is a net data type 
  assign f = a&b;            // assignment statement
endmodule
____________________________________________________________________________


1. Behavioral/Functional design

  • Above code is written in behavioral style.
  • It specifies the functionality of the system wrt to input and output. 
  • In other words, it talks about that for certain inputs, there are corresponding desired output. 
  • The system is taken as black box.  
  • It does not talk about the hardware/circuit of the system. It is up-to a synthesizer to generate the circuit for the desired input-output relation. The circuit could be defined by a single AND gate or by only NAND gates, by only NOR gates. 
  • If a designer want the desired input-output function to be performed by a specific circuit or interconnection of circuits, he/she has to defined the system in structural style.


2. A behavioral design can be defined in the form of:

  • Boolean expression e.g. assign f = a&b;
  • Truth Table using primitives

3. comments in verilog

  • // is used for providing a single line comment.
  • /* */ can be used for providing multiple line comments as in C language



4. Module
e.g. module and_function(f, a, b);
  • This statement is used to define a module.
  • In verilog, a system is defined in the module body.
  • and_function is a name given to this module.
  • (f,a,b) are I/O ports of the designed hardware.
5. wire
  • e.g. wire f;
  • wire is a net data type.
  • Other Net data types are wor, wand, tri, supply0, supply1.
  • All Net data types needs a driver and are continuously driven by them.
  • They don't hold a value like register. 
  • By default, wire is of 1 bit and default value is 'z' (high impedance state) 


6. Assignment
e.g. assign f = a&b;

assign 
  • It is majorly used for behavioral style/data flow coding of combinational circuits. 
  • Can be used for designing sequential circuits but not preferred. 
  • syntax: assign <net type variable> = <net or register or expression>
  • left side of assign statement should be of net type (e.g. wire)
  • right side of assign statement could be register type (e.g. reg) or net type (e.g. wire)  
  • that's why f is declared as wire.
  • All assign statements are executed concurrently.

7. Assignment Classification
  • continuous assignment
    • 'assign'
  • procedural assignment
    • '='      (Blocking assignment)
    • '<='    (Non blocking assignment)

Test Bench
  • In verilog, we built a test bench code along with system design code.
  • It is used for verifying/analyze the result of system design code.
  

____________________________________________________________________________
//Test bench code for 2-input AND Function


module and_test;
  reg x, y;
  wire z;
  and_function F1 (z, x, y); // it is called instantiation
  initial
    begin
      x = 1'b0;   // blocking assignment
      y = 1'b0;   // blocking assignment
      #5 $display("a=%b b=%b f=%b", x,y,z);
       
      x = 1'b0;
      y = 1'b1;
      #5 $display("a=%b b=%b f=%b", x,y,z);
      
      x = 1'b1;
      y = 1'b0;
      #5 $display("a=%b b=%b f=%b", x,y,z);
     
      x = 1'b1;
      y = 1'b1;
      #5 $display("a=%b b=%b f=%b", x,y,z);
      #5 $finish;
    end
endmodule
_________________________________________________________________________________


Output
______________________________

a=0 b=0 f=0
a=0 b=1 f=0
a=1 b=0 f=0
a=1 b=1 f=1
_______________________________



1. Register
  • e.g. reg x, y;
  • reg is Register data type.
  • Other Register data types are integer, real, time.
  • It holds a value.
2. Instantiation
  • Calling a module (or primitive) in another module (or primitive) is called instantiation.
  • Here and_test module called and_function module using  statement (and_function F1 (z, x, y);)
  • It is something similar to calling a function as in C or C++. The difference is that when an instantiation statement is executed, instead of jumping to the called module, it makes a copy of that module in the calling module. It is like adding a similar piece of system/hardware in another system.
  • Multiple instantiation of same module makes multiple copy of that module inside the active module.
  • e.g. and_function F1 (z, x, y); andd_gate is another module, F1 is name give to new piece of hardware added in main module/system (and_test). (z, x, y) are ports of new hardware which are mapped in exact order with ports of called module. so it should be in same order. There is another way too, we see later.

3. Initial Block
  • Initial is one of the type of procedural block. Other is always block.
  • Initial block is majorly used in test bench codes whereas always block is majorly used in system design code.
  • Syntax: <register variable> = <expression>;
  • Initial blocks (and always blocks) contain sequential statements with blocking assignment (=).
  • In other words, statements under Initial (or always) blocks are sequentially executed.
  • In each assignment statements under initial (or always) block, left side should be reg data type variable.
  • That's why x and y are declared reg type variable.
  • only blocking (=) and non-blocking (<=) assignments can be used in initial (or always) blocks.
  • For executing only a single statement under initial (or always) block, there is no need for begin and end.
  • However, for executing a set of statements under initial (or always) block, begin and end is used to grouped them.
  • All statements under initial block are executed only once whereas statements under always block are executed repeatedly to give an impression of an active powered-on hardware.
  • Two or more initial blocks in one module are executed concurrently.

4. Blocking assignment (=)
  • It is called blocking assignment because it blocks the execution of next statement in initial (or always) block. Thus, the blocking statements in initial (or always) block are executed sequentially. However, it doesn't the execution of statements in other initial (or always) blocks.
  • Generally used for designing combinational circuits.
  • When one blocking statement is executed, the updated value of assigned variable is used in subsequent blocking statements. 

 5. $display
  • $display is one of the directives
  • Other directives are $monitor, $finish, $dumpfile, $dumpvars, etc.
  • Syntax: $display("<format>" variables, expressions);
  • It is similar to printf("<format>" variables, expressions) in C.
  • $display displays immediately the values of variables or arithmetic/logical expressions when executed whereas $monitor displays only when there is change in variables. 
6. 
  • %b (or %B) : Binary
  • %d (or %D) : Decimal
  • %s (or %S)  : String
  • %h (or %H) : Hexadecimal
  • %o (or %O) : Octal
  • %e (or %E)  : Real in exponent format (e.g. 5e10)
  • %f (or %F)   : Real in floating point format (e.g. 3.14)
  • %d (or %D)  : Real general in either formats
  • %c (or %C)   : Character
  • %t (or %T)    : Time
  • %v (or %V)   : Strength
  • %m (or %M)  : Hierarchical

7. #5
  • It is explicit delay (simulation time).
8. $finish
  • used to terminate the simulation


2nd Test bench (and_test2) is very similar to above test bench (and_test)
_______________________________________________________________________________
module and_test2;
  reg x, y;
  wire z;
  and_function F1 (z, x, y);
  initial
    begin
      x = 1'b0; y = 1'b0;$display("a=%b b=%b f=%b", x,y,z);
      #5
      x = 1'b0;
      y = 1'b1;
      $display("a=%b b=%b f=%b", x,y,z);
      #5
      x = 1'b1;
      y = 1'b0;
      $display("a=%b b=%b f=%b", x,y,z);
      #5
      x = 1'b1;
      y = 1'b1;
      $display("a=%b b=%b f=%b", x,y,z);
      #5 $finish;
    end

endmodule
________________________________________________________________________________

Output
______________________
a=0 b=0 f=x
a=0 b=1 f=0
a=1 b=0 f=0

a=1 b=1 f=0
______________________ 

Since $display direction print value of z immediately, therefore default value of wire i.e. x is output.
Output is generated after certain gate delay. However, output value is printed immediately in this example.






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