Four Input XNOR Gate Verilog

Four Input XNOR Function in Behavioral style

Design Code
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module XNOR_4input(output f, input [3:0] a); //vector
  wire f = (((a[0]~^a[1])~^a[2])~^a[3]);
endmodule
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Test Bench
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module XNOR_test;
  reg [3:0] x;  // vector 
  wire z;
  XNOR_4input F1 (z, x);
  initial
    begin
      $monitor("%b %b %b %b \t %b", x[0],x[1], x[2], x[3], z);
      x = 4'h0;      // equivalent to 4'b0000
      #5 x = 4'h1; // equivalent to 4'b0001
      #5 x = 4'h2;
      #5 x = 4'h3;
      #5 x = 4'h4;
      #5 x = 4'h5;
      #5 x = 4'h6;
      #5 x = 4'h7;
      #5 x = 4'h8;
      #5 x = 4'h9;
      #5 x = 4'ha;
      #5 x = 4'hb;
      #5 x = 4'hc;
      #5 x = 4'hd;
      #5 x = 4'he;
      #5 x = 4'hf; // equivalent to 4'b1111
      #5 $finish;
    end
endmodule
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output
____________________
0 0 0 0 1
1 0 0 0 0
0 1 0 0 0
1 1 0 0 1
0 0 1 0 0
1 0 1 0 1
0 1 1 0 1
1 1 1 0 0
0 0 0 1 0
1 0 0 1 1
0 1 0 1 1
1 1 0 1 0
0 0 1 1 1
1 0 1 1 0
0 1 1 1 0
1 1 1 1 1
____________________


1. Vector
  • Syntax: <input or output or net or reg identifier> [MSB:LSB] <variable name1, variable name 2, ...>;
  • e.g. input [3:0] a; 
    • It defines a vector variable a with 4 bit wide and a[3] is MSB while a[0] is LSB.
  • e.g. reg [0:3] x, y;
    • It defines two vector variable x and y, each is of 4 bit wide.
    • x[0] is MSB while x[3] is LSB. 
    • individual bits of x can be accessed by its index.


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