4-bit Adder verilog

Four bit parallel adder

Hierarchical Levels
1. 4 Bit Adder using 4 Full Adders


2. Full Adder using two Half Adders
3. Half Adder using logic gates




Structural style (using 4 - full adder)
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module Adder_4bit(input [3:0] A, B, input C0, output [3:0] S, output C4);
  wire C1, C2, C3;
  Full_adder FA0 (S[0], C1, A[0], B[0], C0);
  Full_adder FA1 (S[1], C2, A[1], B[1], C1);
  Full_adder FA2 (S[2], C3, A[2], B[2], C2);
  Full_adder FA3 (S[3], C4, A[3], B[3], C3);
endmodule

module Full_adder(output S, C1, input A, B, C0);
  wire w1, w2, w3;
  Half_Adder HA1 (w1, w2, A, B);
  Half_Adder HA2 (S, w3, w1, C0);
  or_function G1 (C1, w2, w3);
endmodule

module Half_Adder(output S, C, input A, B);
  xor G1 (S, A, B);
  and G2 (C, A, B);
endmodule

module or_function(output f, input a, b); 
  or G1 (f, a, b);
endmodule

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Test Bench

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// Code your testbench here
// or browse Examples
module Adder_test;
  reg [3:0] A, B;
  reg C0;
  wire [3:0] S;
  wire C4;
  Adder_4bit ADD1 (A, B, C0, S, C4);
  initial
    begin
      $display("A3A2A1A0  B3B2B1B0 Cin \t S3S2S1S0 Cout");
      $monitor("%b %b %b %b   %b %b %b %b  %b \t  %b %b %b %b   %b", A[3],A[2],A[1],A[0], B[3], B[2], B[1], B[0], C0, S[3], S[2], S[1], S[0],C4);
      A = 4'h0; B = 4'h0; C0 = 1'b0;
      #5 A = 4'h1; B = 4'h1; C0 = 1'b1;
      #5 A = 4'h0; B = 4'h9; C0 = 1'b1;
      #5 A = 4'h9; B = 4'h9; C0 = 1'b0;
      #5 $finish;
    end
endmodule
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A3A2A1A0 B3B2B1B0 Cin S3S2S1S0 Cout
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 1 0 0 1 1 0
0 0 0 0 1 0 0 1 1 1 0 1 0 0
1 0 0 1 1 0 0 1 0 0 0 1 0 1
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